A transmission-gate-based low-power CMOS half-adder with an antileak sleep-transistor method for industrial sustainability

Abstract

The digital integrated circuits (ICs) are becoming increasingly complex as technology advances daily. Conventional digital ICs often suffer from high transistor counts, large chip areas, and increased power consumption during implementation. Maintaining these parameters at appropriate levels is essential to ensure the efficiency and sustainability of semiconductor technologies. This research proposes a technique using a CMOS transistor and a transmission gate to develop an optimized integrated circuit (IC). It presents a transmission gate approach to replace the existing CMOS implementation in commercially available ICs. Additionally, it introduces a method for reducing leakage power through an improved physical design of a laydown sleep transistor that utilizes the Antileak method. A digital logic circuit of a half-adder cell is implemented using both the conventional CMOS method and the proposed hybrid technique. Comparing the results from both methods, it is evident that the proposed approach is significantly better in terms of cost, power, and area performance. The Antileak laydown sleep transistor reduces leakage power and helps lower overall power consumption. Therefore, the proposed technique for digital ICs offers low-cost, energy-efficient, and area-optimized solutions, supporting sustainability in the semiconductor industry and serving as a viable alternative for future IC development.