An efficient reconfigurable floating point multiplier design for signal processing applications

Abstract

Floating-point arithmetic plays a vital role in modern signal processing applications due to its capability to represent a wide dynamic range of numerical values while maintaining acceptable precision. In this paper, an efficient reconfigurable floating-point multiplier architecture is proposed, specifically designed to meet the performance requirements of signal processing tasks. The proposed design exploits the flexibility of floating-point representations during mantissa computation, enabling optimized arithmetic operations. As a result, the architecture significantly reduces computational complexity, hardware resource utilization, and overall power consumption compared to conventional floating-point multiplier designs. The proposed and existing reconfigurable floating-point multiplier designs were coded in VHDL and implemented on a Kintex-7 XC7K325TFFG900-2 field-programmable gate array (FPGA). The implementation results demonstrate that the proposed modified reconfigurable floating-point multiplier achieves a 55% reduction in look-up table (LUT) utilization, a 47% reduction in critical path delay, and a 56% reduction in power consumption compared to the best existing floating-point multiplier design. The performance metrics such as area, delay, and power show that the proposed design is better compared to existing designs. Overall, the presented reconfigurable floating-point multiplier design offers a promising solution to meet the demanding computational requirements of modern signal processing systems, making it suitable for integration into high-performance digital signal processors and other embedded systems.